The present invention relates generally to integrated circuits and in particular the present invention relates to an integrated circuit having a MOS structure with reduced ON resistance.
Integrated circuits incorporate complex electrical components into a single device. Generally, an integrated circuit comprises a substrate upon which a variety of circuit components are formed wherein each of the circuit components are electrically isolated from each other. For example, the components may include bipolar junction transistors, field effect transistors, etc. Traditionally, integrated circuits found particular application with logic devices and other control circuits that operate at generally low voltages.
Semiconductor material used to make integrated circuits is also effective for handling very high voltages and very high currents. However, traditional high voltage devices are undesired in integrated circuits because the current for their operation generally flows vertically through the substrate to a contact located on the back of the substrate. This design makes it difficult to effectively isolate other devices in the substrate from the high voltage vertical device. These devices are referred to as high voltage vertical devices because the current flows vertically.
More recently, high voltage lateral devices have been developed that are incorporated in integrated circuits. Generally, these high voltage devices are known as lateral devices. A lateral device indicates a device in which the current generally flows horizontal to, or lateral to the device instead of vertical. A high voltage lateral device can be effectively isolated from other circuits or devices in an integrated circuit.
As stated above, integrated circuits are made of semiconductor material. Semiconductor material is material that has a resistance that lies between that of a conductor and an insulator. A common type of semiconductor is the metal-oxide semiconductor (MOS). Semiconductor material is used to make electrical devices that exploit its resistive properties. One common type of semiconductor material is a N-type. N-type semiconductor material is doped with a donor type impurity that generally conducts current via electrons. Another common type of semiconductor material is a P-type. P-type semiconductor material is doped with an acceptor-type impurity that conducts current mainly via hole migration. An example of an electrical device that uses semiconductor material is a transistor. A transistor is a device used to amplify a signal or open and close a circuit. A typical transistor comprises a substrate having layers of varying semiconductor materials that form a source, a drain and a gate. An integrated circuit may comprise a plurality of transistors created from a single substrate to form a circuit.
In a typical semiconductor device constructed as a transistor, the gate typically overlaps a heavily doped drain contact. This results in a high field region where breakdown occurs at relatively low voltages. Breakdown is the failure of the device to perform as designed (i.e. the failure of an isolating region to prevent conduction). Typically, breakdown of a semiconductor transistor occurs at a body/drain junction (when the device is not limited by punch through). To obtain higher break down voltages, double diffused structures are used. Typically, semiconductor devices incorporating double diffused structures have a diffused body (P type for a N type channel) formed in a lightly doped region adjacent to the gate, using the gate edge as a mask. A diffused source is then formed in the body also using the gate edge as part of the mask. The body surface doping sets the threshold voltage. The relatively heavy doping of the body compared to the lightly doped region in which it is formed prevents punch through from drain to source. This allows a higher voltage to be applied to the device before breakdown is reached. An example of a double diffused MOS structure is the double diffused metal-oxide semiconductor (DMOS).
A high voltage lateral MOS structure may incorporate a drain extension as is described in U.S. Pat. Nos. 5,264,719 and 4,823,173. U.S. Pat. Nos. 5,264,719 and 4,823,173 are incorporated herein by reference. The purpose of a drain extension, in general, is to increase breakdown voltage. The drain extension has the effect of decoupling the heavily doped drain contact from a drain edge of an associated gate thereby increasing breakdown voltage. Moreover, under reverse bias conditions, the entire drain extension depletes before electric fields get high enough to cause breakdown. In devices as those disclosed in U.S. Pat. Nos. 5,264,719 and 4,823,173, an ON resistance is encountered in the current path when the device has an activated gate. Generally, the ON resistance consists of the resistance in a channel region under the gate and in the drain extension. Typically, the resistance in the drain extension is the largest term. Generally, the size of the device has a relationship to the ON resistance level. A lower ON resistance per unit area allows the use of smaller dies with reduced costs. Therefore, it is desired, in some high voltage applications, to reduce the ON resistance.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated circuit having a DMOS structure with a reduced ON resistance.
The above-mentioned problems with high voltage MOS structures and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit having a high voltage lateral MOS is disclosed. The high voltage lateral MOS includes a substrate, a top layer of oxide, a island, a drain contact, a source, a gate and a first and second drain extension. The top layer has a first aperture and a second aperture. The first aperture is laterally spaced a predetermined distance from the second aperture. The island is formed in the substrate and is doped with a low density first conductivity type. In addition, the island is positioned between the top layer and the substrate. The drain contact is formed in the island adjacent the first aperture in the top layer and is doped with a high density second conductivity type. The source is formed in the island adjacent the second aperture in the top layer and is doped with a high density second conductivity type. The gate is positioned under the top layer adjacent the P-island and between the source and the drain contact. The first drain extension is of the second conductivity type and is formed in the island. Moreover, the first drain extension is positioned adjacent the top layer extending laterally from under the gate past the drain contact. The first drain extension is positioned around the drain contact. The second drain extension is of the second conductivity type and is also formed in the island. The second drain extension is positioned adjacent the top layer extending laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.
In another embodiment, an integrated circuit having a high voltage lateral DMOS is disclosed. The high voltage lateral DMOS includes a substrate, a top layer of oxide. A Pxe2x88x92 island, a N+ drain contact, a N+ source, a gate and first and second N type drain extensions. The top layer has a first aperture and a second aperture. The first aperture is laterally spaced a predetermined distance from the second aperture. The Pxe2x88x92 island is formed in the substrate. Moreover, the Pxe2x88x92 island is positioned between the top layer and the substrate. The N+ drain contact is formed in the Pxe2x88x92 island adjacent the first aperture of the top layer. The N+ source is formed in the Pxe2x88x92 island adjacent the top layer. At least a portion of the N+ source is positioned adjacent the second aperture of the top layer. The gate is formed in the top layer adjacent the Pxe2x88x92 island. The gate is further positioned between the N+ source and the N+ drain contact. The first drain extension is formed in the Pxe2x88x92 island and is positioned adjacent the top layer extending laterally from under the gate past the drain contact. Moreover, the first drain extension is positioned around the drain contact. The N type second drain extension is formed in the Pxe2x88x92 island and is positioned adjacent the top layer extending laterally under the gate toward the N+ source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased N type doping.
In another embodiment, an integrated circuit having a plurality of high voltage lateral MOS structures includes a substrate, an island, a plurality of source strips, a plurality of drain strips, a plurality of gate strips and a plurality of island contacts. The island has a low density of a first conductivity type and is formed in the substrate. Each source strip is doped with a high density of a second conductivity type and is formed in the island. Each drain strip is doped with a high density of the second conductivity type and is formed in the Pxe2x88x92 island. The plurality of source and drain strips are positioned parallel to each other forming a pattern of alternating source and drain strips in the Pxe2x88x92 island. Each gate strip is positioned adjacent an associated side of a source strip. Each of the plurality of island contacts has a high density of the first conductivity type and is formed in the island. Moreover, each island contact is positioned proximate an end of an associated source channel.
In another embodiment, a method of making an integrated circuit having a high voltage lateral MOS is disclosed. The method comprises introducing a low density impurity of a first conductivity type to a substrate to form an island region, introducing a high density impurity of a second conductivity type in the island region to form a drain contact, introducing a high density impurity of the second conductivity type in the island region to form a source, wherein the source is formed a predetermined lateral distance from the drain, forming a gate on a surface of the island region, wherein the gate is positioned between the drain contact and the source, introducing the second conductivity type impurity in the island region to form a first drain extension, wherein the first drain extension extends laterally from the drain contact to underneath a portion of the gate, further wherein the drain contact is isolated from the island region, and introducing the second conductivity type impurity in the island region to form a second drain extension, wherein the second drain extension extends laterally from a position proximate the source to overlap the first drain extension underneath the gate.